Introduction

QuecOpen^® is a solution where the module acts as the main processor. Constant transition and evolution of both the communication technology and the market highlight its merits. It can help you to:

• Realize embedded applications’ quick development and shorten product R&D cycle
• Simplify circuit and hardware structure design to reduce engineering costs
• Miniaturize products
• Reduce product power consumption
• Apply OTA technology
• Enhance product competitiveness and cost-effectiveness

This document defines FGM842D series in QuecOpen^® solution and describes its air interfaces and hardware interfaces, which are connected with your applications. The document provides a quick insight into interface specifications, RF performance, electrical and mechanical specifications, as well as other related information of the module.

For conciseness purposes, FGM842D and FGM842D-P will hereinafter be referred to collectively as "the module/modules" in parts hereof applicable to both models, and individually as "FGM842D" and "FGM842D-P" in parts hereof referring to the differences between them.

Special Mark

Special Mark:

Mark	Definition
[…]	Brackets ([…]) used after a pin enclosing a range of numbers indicate all pins of the same type. For example, SDIO_DATA[0:3] refers to all four SDIO pins: SDIO_DATA0, SDIO_DATA1, SDIO_DATA2, and SDIO_DATA3.

Product Overview

FGM842D series is high performance MCU Wi-Fi 4 and Bluetooth module supporting IEEE 802.11b/g/n and BLE 5.2 protocols. It provides multiple interfaces including UART, GPIO, SPI, I2C, PWM and ADC for various applications.

It is an SMD module with compact packaging. It includes:

• 160 MHz MCU processor
• Built-in 288 KB RAM and 2 MB Flash
• Support for secondary development

Basic Information:

FGM842D Series	Description
Packaging type	LGA
Pin counts	61
Dimensions	FGM842D: (12.5 +0.3/-0.15) mm × (13.2 +0.3/-0.15) mm × (1.8 ±0.2) mm FGM842D-P: (16.6 +0.3/-0.15) mm × (13.2 +0.3/-0.15) mm × (1.8 ±0.2) mm
Weight	FGM842D: Approx. 1.05 g FGM842D-P: Approx. 1.14 g
Models	FGM842D, FGM842D-P

Key Features

Key Features:

Basic Information	Description
Protocols and Standard	Wi-Fi Protocols: IEEE 802.11b/g/n Bluetooth protocol: BLE 5.2 All hardware components are fully compliant with EU RoHS directive
Power Supply	VBAT Power Supply: 3.0–3.6 V Typ.: 3.3 V
Temperature Ranges 1	Design Option 1: Normal operating temperature: -40 °C to +105 °C Storage temperature: -45 °C to +115 °C Design Option 2: Normal operating temperature: -40 °C to +105 °C Storage temperature: -45 °C to +115 °C
TE-B Kit	FGM842D-TE-B 2
Antenna/Antenna Interfaces
Antenna/Antenna Interfaces	FGM842D3: Pin antenna interface (ANT_WIFI/BT) or RF coaxial connector FGM842D-P: PCB antenna 50 Ω characteristic impedance
Application Interfaces4
Application Interfaces	UART, GPIO, SPI, I2C PWM, ADC

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Functional Diagram

The following figure shows a block diagram of the module and illustrates the major functional parts.

1. FGM842D is provided with one of the two antenna interface designs: pin antenna interface (ANT_WIFI/BT)or RF coaxial connector; FGM842D-P supports PCB antenna. For more details, please contact Quectel TechnicalSupport.
2. The module provides 2 UARTs and 15 GPIO interfaces by default. In the case of multiplexing,it can support interfaces including SPI, I2C, PWM and ADC. For more details, see see Chapter 3.3, GPIO Multiplexing and Chapter 3.4, Application Interfaces.

Application Interfaces

Pin Assignment

1. Keep all RESERVED and unused pins unconnected.
2. All GND pins should be connected to ground.
3. The module provides 2 UARTs and 15 GPIO interfaces by default. In the case of multiplexing, it can support interfaces including SPI, I2C, PWM and ADC. For more details, see Chapter 3.3, GPIO Multiplexing and Chapter 3.4, Application Interfaces.

Pin Description

Parameter description:

Parameter	Description
AIO	Analog Input/Output
DI	Digital Input
DO	Digital Output
DIO	Digital Input/Output
PI	Power Input

DC characteristics include power domain and rated current.

Pin description:

Power Supply and GND Pins:

Pin Name	Pin No.	I/O	Description	DC Characteristics	Comment
VBAT	3	PI	Power supply for the module	Vmax = 3.6V Vmin = 3.0V Vnom = 3.3V	It is recommended to provide a current of at least 0.6A.
GND	FGM842D: 1, 2, 11, 14, 36-46,48-61 FGM842D-p: 1, 2, 11, 14, 36-61	-	-	-	-

Control SIgnal:

Pin Name	Pin No.	I/O	Description	DC Characteristics	Comment
CHIP_EN	8	DI	Enable the module	VBAT	Hardware enable. Internally pulled up to 3.3 V. Active high.

UART Interfaces:

Pin Name	Pin No.	I/O	Description	DC Characteristics	Comment
UART1_TXD	31	DO	UART1 transmit	VBAT	-
UART1_RXD	30	DI	UART1 receive	VBAT	-
UART2_TXD	19	DO	UART2 transmit	VBAT	-
UART2_RXD	20	DI	UART2 receive	VBAT	-

GPIO Interface:

Pin Name	Pin No.	I/O	Description	DC Characteristics	Comment
GPIO20	5	DIO	General-purpose input/output	VBAT	Wakeup
GPIO28	6	DIO	General-purpose input/output	VBAT	Wakeup
GPIO26	12	DIO	General-purpose input/output	VBAT	Wakeup
GPIO24	13	DIO	General-purpose input/output	VBAT	Wakeup
GPIO15	16	DIO	General-purpose input/output	VBAT	Wakeup
GPIO14	17	DIO	General-purpose input/output	VBAT	Wakeup
GPIO17	18	DIO	General-purpose input/output	VBAT	Wakeup
GPIO16	21	DIO	General-purpose input/output	VBAT	Wakeup
GPIO21	22	DIO	General-purpose input/output	VBAT	Wakeup
GPIO22	23	DIO	General-purpose input/output	VBAT	Wakeup
GPIO23	26	DIO	General-purpose input/output	VBAT	Wakeup
GPIO8	32	DIO	General-purpose input/output	VBAT	Wakeup
GPIO6	33	DIO	General-purpose input/output	VBAT	Wakeup
GPIO7	34	DIO	General-purpose input/output	VBAT	Wakeup
GPIO9	35	DIO	General-purpose input/output	VBAT	Wakeup

FGM842D RF Antenna Interface:

Pin Name	Pin No.	I/O	Description	DC Characteristics	Comment
ANT_WIFI/BT	47	AIO	WiFi/Bluetooth	-	50Ω characteristic

RESERVED Pins:

Pin Name	Pin No.	Comment
RESERVED	4, 7, 9, 10, 15, 24, 25, 27-29	Keep them open

GPIO Multiplexing

The module provides 15 GPIO interfaces by default, and can support up to 19 GPIO interfaces in the case of multiplexing. Pins are defined as follows:

GPIO Multiplexing:

Pin Name	Pin No.	Alternate Function 0 (GPIO No.)	Alternate Function 1	Alternate Function 2	Alternate Function 3	Alternate Function 4
GPIO14	17	GPIO14	SPI_CLK	-	-	-
GPIO17	18	GPIO17	SPI_MISO	I2C_SDA	-	-
GPIO16	21	GPIO16	SPI_MOSI	-	-	-
GPIO15	16	GPIO15	SPI_CS	I2C_SCL	-	-
UART2_TXD	19	GPIO0	-	-	-	-
UART2_RXD	20	GPIO1	ADC5	-	-	-
GPIO23	26	GPIO23	-	-	-	-
GPIO6	33	GPIO6	CLK13M	PWM0	JTAG_TCK	-
GPIO7	34	GPIO7	PWM1	JTAG_TMS	-	-
GPIO8	32	GPIO8	PWM2	JTAG_TDI	CLK26M	-
GPIO9	35	GPIO9	PWM3	JTAG_TDO	-	-
GPIO21	22	GPIO21	-	-	-	-
UART1_RXD	30	GPIO10	ADC6	-	-	-
UART1_TXD	31	GPIO11	-	-	-	-
GPIO22	23	GPIO22	-	-	-	-
GPIO28	6	GPIO28	ADC4	-	-	-
GPIO20	5	GPIO20	ADC3	-	-	-
GPIO24	13	GPIO24	LPO_CLK	PWM4	I2C_SCL	ADC2
GPIO26	12	GPIO26	PWM5	I2C_SDA	ADC1	-

1. All GPIOs can be used as sleep interrupts, and the module can immediately enter the working state after waking up.
2. The maximum number of application interfaces enabled through GPIO multiplexing cannot be simultaneously realized. For details on the maximum number of application interfaces supported by the module, please refer to Application Interfaces.

Application Interfaces

UART Interfaces

The module provides 2 UART interfaces by default which can all support full-duplex asynchronous serial communication at a baud rate up to 6 Mbps.

Pin Definition of UART Interfaces:

Pin Name	Pin No.	I/O	Description
UART1_TXD	31	DO	UART1 transmit
UART1_RXD	30	DI	UART1 receive
UART2_TXD	19	DO	UART2 transmit
UART2_RXD	20	DI	UART2 receive

The UART1 can be used for downloading, data transmission and AT command communication with the default baud rate of 115200 bps. The UART1 connection between the module and the MCU is illustrated below.

UART2 can be used as debug UART for outputting partial logs with debugging tools. The default baud rate is 921600 bps. The following is reference design of UART2.

SPI

In the case of multiplexing, the module provides one SPI that supports both master and slave modes. The maximum clock frequency of the interface can reach 20 MHz in slave mode, and 30 MHz in the master mode.

Pin Definition of SPI:

Pin Name	Pin No.	Alternate Function	I/O	Description	Comment
GPIO15	16	SPI_CS	DIO	SPI chip select	In master mode, it is an output signal; In slave mode, it is an input signal.
GPIO14	17	SPI_CLK	DIO	SPI clock	In master mode, it is an output signal; In slave mode, it is an input signal.
GPIO17	18	SPI_MISO	DIO	SPI master-in slave-out	-
GPIO16	21	SPI_MOSI	DIO	SPI master-out slave-in	-

The following figures show the SPI connection between the host and the module:

I2C Interfaces

In the case of multiplexing, the module provides two I2C interfaces which supports the master and slave modes. The interfaces support standard (up to 100 kbps) and fast (up to 400 kbps) modes with 7-bit addressing.

Pin Definition of I2C Interfaces:

Pin Name	Pin No.	Alternate Function	I/O	Description
GPIO17	18	I2C_SDA	OD	I2C serial data
GPIO15	16	I2C_SCL	OD	I2C serial clock
GPIO24	13	I2C_SCL	OD	I2C serial clock
GPIO26	12	I2C_SDA	OD	I2C serial data

Reserve 1–10 kΩ pull-up resistors to VBAT when I2C interface is connected to an external equipment.

PWM Interfaces

In the case of multiplexing, the module supports up to six 32-bit PWM interfaces.

Pin Definition of PWM Interfaces:

Pin Name	Pin No.	Alternate Function	I/O	Description
GPIO6	33	PWM0	DO	PWM0 out
GPIO7	34	PWM1	DO	PWM1 out
GPIO8	32	PWM2	DO	PWM2 out
GPIO9	35	PWM3	DO	PWM3 out
GPIO24	13	PWM4	DO	PWM4 out
GPIO26	12	PWM5	DO	PWM5 out

ADC Interfaces

In the case of multiplexing, the module supports up to six 10-bit ADC interfaces, whose input voltage range is 0–3.3 V. To improve ADC accuracy, surround ADC traces with ground.

Pin Definition of ADC Interfaces:

Pin Name	Pin No.	Alternate Function	I/O	Description
UART2_RXD	20	ADC5	AI	General-purpose ADC interface
UART1_RXD	30	ADC6	AI	General-purpose ADC interface
GPIO28	6	ADC4	AI	General-purpose ADC interface
GPIO20	5	ADC3	AI	General-purpose ADC interface
GPIO24	13	ADC2	AI	General-purpose ADC interface
GPIO26	12	ADC1	AI	General-purpose ADC interface

ADC Features:

Parameter	Min.	Typ.	Max.	Unit
ADC Input Voltage Range	0	-	3.3	V
ADC Resolution	-	10	-	bit

Operating Characteristics

Power Supply

Power supply pin and ground pins of the module are defined in the following table.

Pin Definition of Power Supply and GND Pins:

Pin Name	Pin No.	I/O	Description	Min.	Typ.	Max.	Unit
VBAT	3	PI	Power supply for the module	3.0	3.3	3.6	V
GND	FGM842D: 1, 2, 11, 14, 36-46, 48-61 FGM842D-P: 1, 2, 11, 14, 36-61

Reference Design for Power Supply

The module is powered by VBAT, and it is recommended to use a power supply chip that can provide sufficient current of at least 0.6 A. For better power supply performance, it is recommended to parallel a 22 μF decoupling capacitor, and two filter capacitors (1 μF and 100 nF) near the module’s VBAT pin. C4 is reserved for debugging and not mounted by default. In addition, it is recommended to add a TVS near the VBAT to improve the surge voltage bearing capacity of the module. In principle, the longer the VBAT trace is, the wider it should be.

VBAT reference circuit is shown below:

Turn On

After the module VBAT is powered up, keep the CHIP_EN at high level to realize the automatic startup of the module.

Pin Definition of CHIP_EN:

Pin Name	Pin No.	I/O	Description	Comment
CHIP_EN	8	DI	Enable the module	Hardware enable; Internally pulled up to 3.3 V; Active high.

The turn-on timing is shown below:

Reset

When the voltage of CHIP_EN drops below 0.3 V or pull CHIP_EN down for at least 1 ms, the module can be reset. The reference designs for hardware resetting of the module are shown below. An open collector driving circuit can be used to control the CHIP_EN pin.

Another way to control the CHIP_EN is by using a button directly. When pressing the button, an electrostatic strike may generate from finger. Therefore, a TVS component shall be placed near the button for ESD protection.

The module reset timing is illustrated in the following figure.

RF Performances

Wi-Fi Performances

Wi-Fi Performances

Operating Frequency
2.4 GHz: 2.400–2.4835 GHz
Modulation
DBPSK, DQPSK, CCK, BPSK, QPSK, 16QAM, 64QAM
Operating Mode
AP STA
Encryption Mode
WPA-PSK, WPA2-PSK, WPA3-SAE, AES-128, TRNG
Data Transmission Rate
802.11b: 1 Mbps, 2 Mbps, 5.5 Mbps, 11 Mbps 802.11g: 6 Mbps, 9 Mbps, 12 Mbps, 18 Mbps, 24 Mbps, 36 Mbps, 48 Mbps, 54 Mbps 802.11n: HT20 (MCS 0–MCS 7)
Condition (VBAT = 3.3 V; Temp.: 25 °C)		EVM	Typ.; Unit: dBm, Tolerance: ±2 dB
			Transmit Power	Receiver Sensitivity
2.4 GHz	802.11b @ 1 Mbps	≤ 35 %	18	-98
	802.11b @ 11 Mbps		18	-90
	802.11g @ 6 Mbps	≤ -5 dB	16	-90
	802.11g @ 54 Mbps	≤ -25 dB	15	-76
	802.11n, HT20 @ MCS 0	≤ -5 dB	15	-90
	802.11n, HT20 @ MCS 7	≤ -27 dB	14	-72

Bluetooth Performances

Bluetooth Performances

Operating Frequency
2.400–2.4835 GHz
Modulation
GFSK
Operating Mode
BLE
Condition (VBAT = 3.3 V; Temp.: 25 °C)	Typ.; Unit: dBm, Tolerance: ±2 dB
	Transmit Power	Receiver Sensitivity
BLE (1 Mbps)	6	-96
BLE (2 Mbps)	6	-94
BLE (S = 2)	6	-96
BLE (S = 8)	6	-101

Antenna/Antenna Interfaces

FGM842D is provided with one of the two antenna interface designs: pin antenna interface (ANT_WIFI/BT) or RF coaxial connector. The RF coaxial connector is not available when the module is designed with ANT_WIFI/BT antenna interface; FGM842D-P supports PCB antenna. The impedance of antenna port is 50 Ω.

Appropriate antenna type and design should be used with matched antenna parameters according to specific application. It is required to perform a comprehensive functional test for the RF design before mass production of terminal products. The entire content of this chapter is provided for illustration only. Analysis, evaluation and determination are still necessary when designing target products.

FGM842D Pin Antenna Interface (ANT_WIFI/BT) ⁵

ANT_WIFI/BT Pin Definition:

Pin Name	Pin No.	I/O	Description	Comment
ANT_WIFI/BT	47	AIO	Wi-Fi/Bluetooth antenna interface	50 Ω characteristic impedance.

Antenna Design Requirements

Antenna Design Requirements:

Type	Requirement
Frequency range (GHz)	2.400–2.4835
Cable insertion loss (dB)	< 1
VSWR	≤ 2 (typ.)
Gain (dBi)	1 (typ.)
Maximum input power (W)	50
Input impedance (Ω)	50
Polarization	Vertical

RF Signal Trace Routing Guidelines

When designing the PCB, control the characteristic impedance of all RF signal traces to 50 Ω. In general, the impedance of RF traces is determined by the dielectric constant of the material, trace width (W), spacing to ground (S), and the height of the reference ground plane (H). Typical PCB impedance control methods are microstrip and coplanar waveguide. To illustrate the design principles, the following figures show microstrip and coplanar waveguide structures configured for 50 Ω characteristic impedance.

To ensure RF performance and reliability, follow the principles below in RF layout design:

• Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
• The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
• The distance between the RF pins and the RF connector should be as short as possible and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135°.
• There should be clearance under the signal pin of the antenna connector or solder joint.
• The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be at least twice the width of RF signal traces (2 × W).
• Keep RF traces away from interference sources (such as DC-DC, (U)SIM/USB/SDIO high frequency digital signals, display signals, and clock signals), and avoid intersection and paralleling between traces on adjacent layers.

For more details about RF layout, see RF-Layout-Application-Note.

RF Connector Recommendation

If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by Hirose.

U.FL-LP series mated plugs listed in the following figure can be used to match the U.FL-R-SMT connector.

The following figure describes the space factor of mated connectors.

For more details, please visit http://www.hirose.com.

FGM842D RF Coaxial Connector ⁶

Receptacle Specifications

The mechanical dimensions of the receptacle supported by the module are as follows.

Major Specifications of the RF Connector:

Item	Specification
Nominal Frequency Range	DC to 6 GHz
Nominal Impedance	50 Ω
Temperature Rating	-40 °C to +105 °C
Voltage Standing Wave Ratio (VSWR)	Meet the requirements of: Max. 1.3 (DC–3 GHz) Max. 1.45 (3–6 GHz)

Antenna Connector Installation

The mated plug listed in the following figure can be used to match the connector.

Recommended RF Connector Installation

The pictures for plugging in a coaxial cable plug is shown below, θ = 90° is acceptable, while θ ≠ 90° is not.

The pictures of pulling out the coaxial cable plug is shown below, θ = 90° is acceptable, while θ ≠ 90° is not.

The pictures of installing the coaxial cable plug with a jig is shown below, θ = 90° is acceptable, while θ ≠ 90° is not.

Recommended Manufacturers of RF Connector and Cable

RF connectors and cables by I-PEX are recommended. For more details, visit https://www.i-pex.com.

FGM842D-P PCB Antenna

The performance of the PCB antenna depends on the entire product, including the motherboard, case, other RF signals, etc., and it is recommended to verify it at the early stage of design. To ensure the performance and reliability when designed with PCB antenna, follow the basic principles below for module’s placement and layout:

1. The module should be placed on the edge of the motherboard.
2. On the motherboard, all PCB layers under the PCB antenna should be designed as keepout areas.
3. On the motherboard, ensure a minimum clearance of 16 millimeters between the PCB antenna and vias, traces, copper pour area, and other components, such as connectors, Ethernet ports and any metal components.
4. If using a plastic case, ensure a minimum clearance of 10 millimeters between the PCB antenna and the plastic case. If using a metal case, it is recommended to use an external antenna.

If any of the above principles cannot be guaranteed, it is advisable to explore alternative antenna solutions for the module or seek assistance from the Quectel Antenna Team, who can offer design assistance and recommend suitable external antennas. Please feel free to contact Quectel Technical Support if necessary.

Antenna Design Requirements

Antenna Design Requirements

Antenna Type	Requirement
Pin Antenna Interface RF Coaxial Connector	Frequency Range: 2.400–2.4835 GHz VSWR: ≤ 2 (Typ.) Gain: 1 dBi (Typ.) Max. Input Power: 50 W Input Impedance: 50 Ω Vertical Polarization Cable Insertion Loss: < 1 dB
PCB Antenna	Frequency Range: 2.400–2.5000 GHz VSWR: ≤ 3.2 Gain: 1.5 dBi Efficiency: 42 % Input Impedance: 50 Ω

Electrical Characteristics & Reliability

Absolute Maximum Ratings

Absolute Maximum Ratings (Unit: V):

Parameter	Min.	Max.
VBAT	-0.3	3.6
Voltage at Digital Pins	-0.3	3.6
Input Voltage at ADC[1:6]	0	3.6

Power Supply Ratings

Module Power Supply Ratings (Unit: V)

Parameter	Description	Condition	Min.	Typ.	Max.
VBAT	Power supply for the module	The actual input voltages must be kept between the minimum and maximum values.	3.0	3.3	3.6

Power Consumption

Wi-Fi Power Consumption

Power Consumption in Non-signaling Mode (Typ.; Unit: mA)

Condition			IVBAT
2.4 GHz	802.11b	Tx 1 Mbps @ 18 dBm	267.11
		Tx 11 Mbps @ 18 dBm	271.50
	802.11g	Tx 6 Mbps @ 16 dBm	246.18
		Tx 54 Mbps @ 15 dBm	245.68
	802.11n	Tx HT20 MCS 0 @ 15 dBm	245.40
		Tx HT20 MCS 7 @ 14 dBm	233.00

Bluetooth Power Consumption

Power Consumption in Non-signaling Mode (Typ.; Unit: mA)

Condition	IVBAT
BLE (1 Mbps)	90.54
BLE (2 Mbps)	65.13
BLE (S = 2)	81.73
BLE (S = 8)	103.67

Digital I/O Characteristics

VBAT I/O Requirements (Unit: V)

Parameter	Description	Min.	Max.
VIH	High-level input voltage	0.7 × VBAT	VBAT
VIL	Low-level input voltage	0	0.3 × VBAT
VOH	High-level output voltage	0.9 × VBAT	-
VOL	Low-level output voltage	-	0.1 × VBAT

ESD Protection

Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design.

ESD Characteristics (Unit: kV):

Model	Test Result	Standard
Human Body Model (HBM)	±2	ANSI/ESDA/JEDEC JS-001-2017
Charged Device Model (CDM)	±0.5	ANSI/ESDA/JEDEC JS-002-2018

Mechanical Information

This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeters (mm), and the dimensional tolerances are ±0.2 mm unless otherwise specified.

Mechanical Dimensions

The module's coplanarity standard: ≤ 0.13 mm.

Top and Bottom Views

1. Images above are for illustrative purposes only and may differ from the actual module. For authentic appearance and label, refer to the module received from Quectel.
2. The RF coaxial connector is not mounted on the FGM842D when using pin antenna interface (ANT_WIFI/BT).

Storage, Manufacturing & Packaging

Storage Conditions

The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below.

1. Recommended Storage Condition: the temperature should be 23 ±5 °C and the relative humidity should be 35–60 %.

2. Shelf life (in a vacuum-sealed packaging): 12 months in Recommended Storage Condition.

3. Floor life: 168 hours [^7] in a factory where the temperature is 23 ±5 °C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet).

   [^7]: This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not unpack the modules in large quantities until they are ready for soldering.

4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

   • The module is not stored in Recommended Storage Condition;
   • Violation of the third requirement mentioned above;
   • Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
   • Before module repairing.

5. If needed, the pre-baking should follow the requirements below:

   • The module should be baked for 24 hours at 120 ±5 °C;
   • The module must be soldered to PCB within 24 hours after the baking, otherwise it should be put in a dry environment such as in a dry cabinet.

1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden.
2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure.
3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules.

Manufacturing and Soldering

Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.15–0.18 mm. For more details, see Moudule-Stencil-Design-Requirements.

The recommended peak reflow temperature should be 235–246 ºC, with 246 ºC as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below.

Recommended Thermal Profile Parameters：

Factor	Recommended Value
Soak Zone
Ramp-to-soak slope	0–3 °C/s
Soak time (between A and B: 150 °C and 200 °C)	70–120 s
Reflow Zone
Ramp-up slope	0–3 °C/s
Reflow time (D: over 217 °C)	40–70 s
Max. temperature	235–246 °C
Cool-down slope	-3–0 °C/s
Reflow Cycle
Max. reflow cycle	1

1. The above profile parameter requirements are for the measured temperature of solder joints. Both the hottest and coldest spots of solder joints on the PCB should meet the above requirements.
2. During manufacturing and soldering, or any other processes that may contact the module directly, NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted.
3. The shielding can for the module is made of Cupro-Nickel base material. It is tested that after 12 hours’ Neutral Salt Spray test, the laser engraved label information on the shielding can is still clearly identifiable and the QR code is still readable, although white rust may be found.
4. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module.
5. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module.
6. Avoid using materials that contain mercury (Hg), such as adhesives, for module processing, even if the materials are RoHS compliant and their mercury content is below 1000 ppm (0.1 %).
7. Corrosive gases may corrode the electronic components inside the module, affecting their reliability and performance, and potentially leading to a shortened service life that fails to meet the designed lifespan. Therefore, do not store or use unprotected modules in environments containing corrosive gases such as hydrogen sulfide, sulfur dioxide, chlorine, and ammonia.
8. Due to the complexity of the SMT process, please contact Quectel Technical Support in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document[4].

Packaging Specification

This chapter outlines the key packaging parameters and processes. All figures below are for reference purposes only, as the actual appearance and structure of packaging materials may vary in delivery.

The modules are packed in a tape and reel packaging as specified in the sub-chapters below.

Carrier Tape

Carrier tape dimensions are illustrated in the following figure and table:

FGM842D Carrier Tape Dimension Table (Unit: mm):

W	P	T	A0	B0	K0	K1	F	E
32	24	0.4	13.6	12.9	2.3	3.2	14.2	1.75

FGM842D-P Carrier Tape Dimension Table (Unit: mm):

W	P	T	A0	B0	K0	K1	F	E
32	24	0.4	13.6	17	2.3	3.2	14.2	1.75

Plastic Reel

Plastic reel dimensions are illustrated in the following figure and table:

Plastic Reel Dimension Table (Unit: mm):

øD1	øD2	W
380	100	32.5

Mounting Direction

Packaging Process

Packaging Process

Image	Description
	Place the modules onto the carrier tape cavity and cover them securely with cover tape. Wind the heat-sealed carrier tape onto a plastic reel and apply a protective tape for additional protection. 1 plastic reel can pack 1000 modules.
	Place the packaged plastic reel, humidity indicator card and desiccant bag into a vacuum bag, and vacuumize it.
	Place the vacuum-packed plastic reel into a pizza box.
	Place the 4 packaged pizza boxes into 1 carton and seal it. 1 carton can pack 4000 modules.

Appendix References

Reference Documents:

Document Name
[1] Quectel_FGM842D_Series_TE-B_User_Guide
[2] Quectel_RF_Layout_Application_Note
[3] Quectel_Module_Stencil_Design_Requirements
[4] Quectel_Module_SMT_Application_Note

Terms and Abbreviations

Abbreviation	Description
ADC	Analog-to-Digital Converter
AES	Advanced Encryption Standard
AP	Access Point
BLE	Bluetooth Low Energy
BPSK	Binary Phase Shift Keying
CCK	Complementary Code Keying
CDM	Charged Device Model
DSSS	Direct Sequence Spread Spectrum
ESD	Electrostatic Discharge
EVM	Error Vector Magnitude
GFSK	Gauss frequency Shift Keying
GND	Ground
GPIO	General-Purpose Input/Output
HBM	Human Body Model
HT	High Throughput
I/O	Input/Output
I2C	Inter-Integrated Circuit
IEEE	Institute of Electrical and Electronics Engineers
JTAG	Joint Test Action Group
LCC	Leadless Chip Carrier (package)
Mbps	Million Bits Per Second
MCU	Microcontroller Unit
MISO	Master In Slave Out
MOSI	Master Out Slave In
OTA	Over-the-Air
PCB	Printed Circuit Board
PSK	Pre-Shared Key
PWM	Pulse Width Modulation
QAM	Quadrature Amplitude Modulation
QPSK	Quadrature Phase Shift Keying
RAM	Random Access Memory
RF	Radio Frequency
RoHS	Restriction of Hazardous Substances
SAE	Simultaneous Authentication of Equals
SMD	Surface Mount Device
SMT	Surface Mount Technology
SPI	Serial Peripheral Interface
STA	Station
TRNG	True Random Number Generator
TVS	Transient Voltage Suppressor
Tx	Transmit
UART	Universal Asynchronous Receiver/Transmitter
(U)SIM	(Universal) Subscriber Identity Module
VIH	High-level Input Voltage
VIL	Low-level Input Voltage
Vmax	Maximum Voltage
Vmin	Minimum Voltage
Vnom	Nominal Voltage Value
VOH	High-level Output Voltage
VOL	Low-level Output Voltage
VSWR	Voltage Standing Wave Ratio
WPA	Wi-Fi Protected Access

1. Within the operating temperature range, the module’s related performance meets IEEE and Bluetooth specifications.↩

2. For more details about the TE-B, see TE-B User Guide.↩

3. FGM842D is provided with one of the two antenna interface designs. For more details, please contact Quectel Technical Support.↩

4. For more details about the interfaces, see Chapter 3.3, GPIO Multiplexing and Chapter 3.4, Application Interfaces.↩

5. FGM842D is provided with one of the two antenna interface designs. For more details, contact Quectel Technical Support.↩

6. FGM842D is provided with one of the two antenna interface designs. For more details, contact Quectel Technical Support.↩

TE-B User Guide

WiFi Development Guide